BlockDiagram

EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0GLB sys_rst_pin I 1 sys_rst_s  RESET 
1GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk
2GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn
3GLB fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s
4A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin IO 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
5A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin IO 0:63 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
6A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin O 0:12 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
7A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin O 0:1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
8A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
9A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
10A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
11A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin O 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
12A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
13A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
14B fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX
15B fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX
16C sys_clk_pin I 1 dcm_clk_s  CLK 
17C fpga_0_net_gnd_1_pin O 1 net_gnd
18C fpga_0_net_gnd_2_pin O 1 net_gnd
19C fpga_0_net_gnd_3_pin O 1 net_gnd
20C fpga_0_net_gnd_4_pin O 1 net_gnd
21C fpga_0_net_gnd_5_pin O 1 net_gnd
22C fpga_0_net_gnd_6_pin O 1 net_gnd
23C fpga_0_net_gnd_pin O 1 net_gnd
24D fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK 
25E ledDebug_pin O 0:3 ledDebug