Printable Version



Overview TOP


Overview
Generated on Thu Jan 10 13:46:46 2008
EDK Version 9.1.02
FPGA Family virtex2p
Device xc2vp30ff896-7
# IP Instantiated 15
# Processors 1
# Busses 3



Block Diagram TOP


BlockDiagram



External Ports TOP


EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0GLB sys_rst_pin I 1 sys_rst_s  RESET 
1GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk
2GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn
3GLB fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s
4A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin IO 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
5A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin IO 0:63 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
6A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin O 0:12 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
7A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin O 0:1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
8A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
9A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
10A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
11A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin O 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
12A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
13A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
14B fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX
15B fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX
16C sys_clk_pin I 1 dcm_clk_s  CLK 
17C fpga_0_net_gnd_1_pin O 1 net_gnd
18C fpga_0_net_gnd_2_pin O 1 net_gnd
19C fpga_0_net_gnd_3_pin O 1 net_gnd
20C fpga_0_net_gnd_4_pin O 1 net_gnd
21C fpga_0_net_gnd_5_pin O 1 net_gnd
22C fpga_0_net_gnd_6_pin O 1 net_gnd
23C fpga_0_net_gnd_pin O 1 net_gnd
24D fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK 
25E ledDebug_pin O 0:3 ledDebug



Processors TOP

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor


microblaze_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
MASTER DLMB LMB dlmb dlmb_cntlr
MASTER ILMB LMB ilmb ilmb_cntlr
MASTER DOPB OPB mb_opb NA
MASTER IOPB OPB mb_opb NA


General
IP Core microblaze
Version 6.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex2p
C_INSTANCE
Instance Name
microblaze_0
C_DCACHE_BASEADDR
D-Cache Base Address
0x00000000
C_DCACHE_HIGHADDR
D-Cache High Address
0x3FFFFFFF
C_ICACHE_BASEADDR
I-Cache Base Address
0x00000000
C_ICACHE_HIGHADDR
I-Cache High Address
0x3FFFFFFF
C_ADDR_TAG_BITS
Number of I-Cache Address Tag Bits
0
C_ALLOW_DCACHE_WR
Enable D-Cache Writes
1
C_ALLOW_ICACHE_WR
Enable I-Cache Writes
1
C_AREA_OPTIMIZED
Select implementation to optimize area (with lower instruction throughput)
0
C_CACHE_BYTE_SIZE
Size of the I-Cache in Bytes
8192
C_DATA_SIZE
C_DATA_SIZE
32
C_DCACHE_ADDR_TAG
Number of D-Cache Address Tag Bits
0
C_DCACHE_BYTE_SIZE
Size of D-Cache in Bytes
8192
C_DCACHE_LINE_LEN
Data Cache Line Length
4
C_DCACHE_USE_FSL
Enable Xilinx Cache Links for D-Cache
1
C_DEBUG_ENABLED
Enable MicroBlaze Debug Module Interface
0
C_DIV_ZERO_EXCEPTION
Enable Integer Divide-by-zero Exception
0
C_DOPB_BUS_EXCEPTION
Enable Data-side OPB Exception
0
C_DYNAMIC_BUS_SIZING
C_DYNAMIC_BUS_SIZING
1
C_D_LMB
Use data-side Local Memory Bus
1
C_D_OPB
Use data-side On-Chip Peripheral Bus
1
C_EDGE_IS_POSITIVE
Sense Interrupt on Rising vs. Falling Edge
1
C_FPU_EXCEPTION
Enable Floating Point Unit Exceptions
0
C_FSL_DATA_SIZE
FSL Link Data Width
32
C_FSL_LINKS
Number of FSL Links
0
 
Name Value
C_ICACHE_LINE_LEN
Instructon Cache Line Length
4
C_ICACHE_USE_FSL
Enable Xilinx Cache Links for I-Cache
1
C_ILL_OPCODE_EXCEPTION
Enable Illegal Instruction Exception
0
C_INTERRUPT_IS_EDGE
Sense Interrupt on Edge vs. Level
0
C_IOPB_BUS_EXCEPTION
Enable Instruction-side OPB Exception
0
C_I_LMB
Use instruction-side Local Memory Bus
1
C_I_OPB
Use instruction-side On-Chip Peripheral Bus
1
C_NUMBER_OF_PC_BRK
Number of PC Breakpoints
1
C_NUMBER_OF_RD_ADDR_BRK
Number of Read Address Watchpoints
0
C_NUMBER_OF_WR_ADDR_BRK
Number of Write Address Watchpoints
0
C_OPCODE_0x0_ILLEGAL 0
C_PVR
Specifies Processor Version Register
0
C_PVR_USER1
Specify USER1 Bits in Processor Version Register
0x00
C_PVR_USER2
Specify USER2 Bits in Processor Version Registers
0x00000000
C_RESET_MSR
Specify Reset Value for Select MSR Bits
0x00000000
C_SCO
C_SCO
0
C_UNALIGNED_EXCEPTIONS
Enable Unaligned Data Exception
0
C_USE_BARREL
Enable Barrel Shifter
0
C_USE_DCACHE
Enable Data Cache
0
C_USE_DIV
Enable Integer Divider
0
C_USE_FPU
Enable Floating Point Unit
0
C_USE_HW_MUL
Enable Integer Multiplier
1
C_USE_ICACHE
Enable Instruction Cache
0
C_USE_MSR_INSTR
Enable Additional Machine Status Register Instructions
1
C_USE_PCMP_INSTR
Enable Pattern Comparator
1
 
MEMORY MAP
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
D I BASE HIGH MODULE
  0x00000000 0x0000FFFF C_BASEADDR:C_HIGHADDRdlmb_cntlr
  0x00000000 0x0000FFFF C_BASEADDR:C_HIGHADDRilmb_cntlr
0x40600000 0x4060FFFF C_BASEADDR:C_HIGHADDRRS232_Uart_1
0x60000000 0x6FFFFFFF C_MEM0_BASEADDR:C_MEM0_HIGHADDRDDR_256MB_32MX64_rank1_row13_col10_cl2_5
0x7A400000 0x7A40FFFF C_BASEADDR:C_HIGHADDRopb_evoblock_0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1010 13696 7
Slice Flip Flops 1253 27392 4
4 input LUTs 1662 27392 6
IOs 1338 NA NA
bonded IOBs 0 556 0
MULT18X18s 3 136 2





Busses TOP
dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'


dlmb IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 LMB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 DLMB
SLAVE dlmb_cntlr SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH
Active High External Reset
0
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 2 27392 0
IOs 211 NA NA
bonded IOBs 0 556 0


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'


ilmb IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 LMB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 ILMB
SLAVE ilmb_cntlr SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH
Active High External Reset
0
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 2 27392 0
IOs 211 NA NA
bonded IOBs 0 556 0


mb_opb   On-chip Peripheral Bus (OPB) 2.0
OPB_V20 On-Chip Peripheral Bus V2.0 with OPB Arbiter (OPB_V20)


mb_opb IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 OPB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 DOPB
MASTER microblaze_0 IOPB
SLAVE RS232_Uart_1 SOPB
SLAVE DDR_256MB_32MX64_rank1_row13_col10_cl2_5 SOPB
SLAVE opb_evoblock_0 SOPB


General
IP Core opb_v20
Version 1.10.c
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
Base Address
0xFFFFFFFF
C_HIGHADDR
High Address
0x00000000
C_DEV_BLK_ID
Device Block ID
0
C_DEV_MIR_ENABLE
Enable Module Identification Register (MIR)
0
C_DYNAM_PRIORITY
Use Dynamic Instead of Fixed Priority Bus Arbitration
0
C_EXT_RESET_HIGH
External Reset High
0
C_NUM_MASTERS
Number of Bus Masters
2
 
Name Value
C_NUM_SLAVES
Number of Bus Slaves
3
C_OPB_AWIDTH
OPB Address Bus Width
32
C_OPB_DWIDTH
OPB Data Bus Width
32
C_PARK
Support Bus Parking
0
C_PROC_INTRFCE
Enable Access To OPB Arbiter Registers
0
C_REG_GRANTS
Use Registered Instead of Combinational Grant Outputs
1
C_USE_LUT_OR
Use Only LUTs for OR Structure
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 99 13696 0
Slice Flip Flops 11 27392 0
4 input LUTs 169 27392 0
IOs 444 NA NA
bonded IOBs 0 556 0





Memory TOP
lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.


lmb_bram IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
TARGET PORTA XIL ilmb_port ilmb_cntlr
TARGET PORTB XIL dlmb_port dlmb_cntlr


General
IP Core bram_block
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex2p
C_MEMSIZE
Size of BRAM(s) in Bytes
0x10000
C_NUM_WE
Number of Byte Write Enables
4
C_PORT_AWIDTH
Address Width of Port A and B
32
C_PORT_DWIDTH
Data Width of Port A and B
32
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 0 13696 0
IOs 206 NA NA
bonded IOBs 0 556 0
BRAMs 32 136 23





Memory Controllers TOP
dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus


dlmb_cntlr IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
INITIATOR BRAM_PORT XIL dlmb_port lmb_bram
SLAVE SLMB LMB dlmb microblaze_0


General
IP Core lmb_bram_if_cntlr
Version 2.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x0000FFFF
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_MASK
LMB Address Decode Mask
0x20400000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 5 27392 0
IOs 209 NA NA
bonded IOBs 0 556 0


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus


ilmb_cntlr IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
INITIATOR BRAM_PORT XIL ilmb_port lmb_bram
SLAVE SLMB LMB ilmb microblaze_0


General
IP Core lmb_bram_if_cntlr
Version 2.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x0000FFFF
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_MASK
LMB Address Decode Mask
0x20400000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 5 27392 0
IOs 209 NA NA
bonded IOBs 0 556 0





Peripherals TOP
DDR_256MB_32MX64_rank1_row13_col10_cl2_5   OPB DDR SDRAM Controller
On-Chip Peripheral Bus Double Data Rate Synchronous DRAM (OPB DDR SDRAM) controller


DDR_256MB_32MX64_rank1_row13_col10_cl2_5 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Device_Clk90_in I 1 ddr_dev_clk_90_s
2 Device_Clk90_in_n I 1 ddr_dev_clk_90_s_n
3 Device_Clk I 1 ddr_dev_clk_s
4 Device_Clk_n I 1 ddr_dev_clk_s_n
5 DDR_Clk90_in I 1 ddr_clk_90_s
6 DDR_Clk90_in_n I 1 ddr_clk_90_n_s
7 DDR_DQS IO 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
8 DDR_DQ IO 0:63 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
9 DDR_Addr O 0:12 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
10 DDR_BankAddr O 0:1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
11 DDR_CASn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
12 DDR_CKE O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
13 DDR_CSn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
14 DDR_RASn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
15 DDR_WEn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
16 DDR_DM O 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
17 DDR_Clk O 0:3 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
18 DDR_Clkn O 0:3 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_ddr
Version 2.00.c
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex2p
C_MEM0_BASEADDR
Base Address of Bank 0
0x60000000
C_MEM0_HIGHADDR
High Address of Bank 0
0x6FFFFFFF
C_MEM1_BASEADDR
Base Address of Bank 1
0xFFFFFFFF
C_MEM1_HIGHADDR
High Address of Bank 1
0x00000000
C_MEM2_BASEADDR
Base Address of Bank 2
0xFFFFFFFF
C_MEM2_HIGHADDR
High Address of Bank 2
0x00000000
C_MEM3_BASEADDR
Base Address of Bank 3
0xFFFFFFFF
C_MEM3_HIGHADDR
High Address of Bank 3
0x00000000
C_DDR_ASYNC_SUPPORT
Supports Asynchronous DDR Clock
1
C_DDR_AWIDTH
Address Width of DDR Memory
13
C_DDR_BANK_AWIDTH
Bank Address Width of DDR Memory
2
C_DDR_CAS_LAT
CAS Latency
2
C_DDR_COL_AWIDTH
Column Address Width of DDR Memory
10
C_DDR_DWIDTH
Cumulative Data Width of DDR Memory
64
C_DDR_TMRD
TMRD
20000
C_DDR_TRAS
TRAS
60000
C_DDR_TRC
TRC
90000
 
Name Value
C_DDR_TRCD
TRCD
30000
C_DDR_TREFC
TREFC
70300000
C_DDR_TREFI
TREFI
7800000
C_DDR_TRFC
TRFC
100000
C_DDR_TRP
TRP
30000
C_DDR_TRRD
TRRD
20000
C_DDR_TWR
TWR
20000
C_DDR_TWTR
TWTR
1
C_EXTRA_TSU
Support Extra Setup Time
0
C_INCLUDE_BURST_SUPPORT
Support OPB Burst Mode
0
C_NUM_BANKS_MEM
Number of DDR Memory Bank
1
C_NUM_CLK_PAIRS
Number of Generated DDR Clock Pairs
4
C_OPB_AWIDTH
OPB Address Bus Width
32
C_OPB_CLK_PERIOD_PS
OPB Clock Period
20000
C_OPB_DWIDTH
OPB Data Bus Width
32
C_REG_DIMM
Support Registered DIMM
0
C_SIM_INIT_TIME_PS
DDR Initialization Time for Simulation
200000000
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1303 13696 9
Slice Flip Flops 1143 27392 4
4 input LUTs 1114 27392 4
IOs 368 NA NA
bonded IOBs 0 556 0


RS232_Uart_1   OPB UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for OPB bus.


RS232_Uart_1 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 RX I 1 fpga_0_RS232_Uart_1_RX
2 TX O 1 fpga_0_RS232_Uart_1_TX
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_uartlite
Version 1.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
Base Address
0x40600000
C_HIGHADDR
High Address
0x4060FFFF
C_BAUDRATE
UART Lite Baud Rate
115200
C_CLK_FREQ
OPB Clock Frequency
50000000
C_DATA_BITS
Number of Data Bits in a Serial Frame
8
C_ODD_PARITY
Parity Type
0
C_OPB_AWIDTH
OPB Address Bus Width
32
C_OPB_DWIDTH
OPB Data Bus Width
32
C_USE_PARITY
Use Parity
0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 49 13696 0
Slice Flip Flops 59 27392 0
4 input LUTs 93 27392 0
IOs 112 NA NA
bonded IOBs 0 556 0


opb_evoblock_0



opb_evoblock_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
1 ledDebug O 0:3 ledDebug
Bus Interfaces
MASTERSHIP NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_evoblock
Version 1.00.a
Driver API
Parameters
These are parameters set for this module.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
C_BASEADDR 0x7A400000
C_HIGHADDR 0x7A40FFFF
C_OPB_AWIDTH 32
C_OPB_DWIDTH 32
C_USER_ID_CODE 3
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 8437 13696 61
Slice Flip Flops 6773 27392 24
4 input LUTs 9584 27392 34
IOs 113 NA NA
bonded IOBs 0 556 0
BRAMs 1 136 0





IP TOP

dcm_0   Digital Clock Manager (DCM)
The digital clock manager module is a wrapper around the DCM primitive which allows it to be used in the EDK tool suite.


dcm_0 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 CLKIN I 1 dcm_clk_s
2 CLKFB I 1 ddr_dev_clk_s
3 RST I 1 net_gnd
4 CLK0 O 1 ddr_dev_clk_s
5 CLK90 O 1 ddr_dev_clk_90_s
6 CLKDV O 1 sys_clk_s
7 LOCKED O 1 dcm_0_lock


General
IP Core dcm_module
Version 1.00.c
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex2p
C_CLK0_BUF
Insert a BUFG for CLK0
TRUE
C_CLK180_BUF
Insert a BUFG for CLK180
FALSE
C_CLK270_BUF
Insert a BUFG for CLK270
FALSE
C_CLK2X180_BUF
Insert a BUFG for CLK2X180
FALSE
C_CLK2X_BUF
Insert a BUFG for CLK2X
FALSE
C_CLK90_BUF
Insert a BUFG for CLK90
TRUE
C_CLKDV_BUF
Insert a BUFG for CLKDV
TRUE
C_CLKDV_DIVIDE
CLKDV Divisor
2.000000
C_CLKFB_BUF
Insert a BUFG for CLKFB
FALSE
C_CLKFX180_BUF
Insert a BUFG for CLKFX180
FALSE
C_CLKFX_BUF
Insert a BUFG for CLKFX
FALSE
C_CLKFX_DIVIDE
Divisor for the CLKFX Output
1
C_CLKFX_MULTIPLY
Multiply Value of the CLKFX Output
4
 
Name Value
C_CLKIN_BUF
Insert a BUFG for CLKIN
FALSE
C_CLKIN_DIVIDE_BY_2
CLKIN Divide By 2
FALSE
C_CLKIN_PERIOD
Input Clock Period
10.000000
C_CLKOUT_PHASE_SHIFT
Controls Use of Phase Shift
NONE
C_CLK_FEEDBACK
Clock Feedback Input
1X
C_DESKEW_ADJUST
Amount of Delay in the Feedback Path
SYSTEM_SYNCHRONOUS
C_DFS_FREQUENCY_MODE
Digital Frequency Synthesizer Clock Frequency Mode
LOW
C_DLL_FREQUENCY_MODE
Delay Locked Loop Frequency Mode
LOW
C_DSS_MODE
DSS Mode
NONE
C_DUTY_CYCLE_CORRECTION
Duty Cycle Correction
TRUE
C_EXT_RESET_HIGH
Reset Polarity
1
C_PHASE_SHIFT
Phase Shift
0
C_STARTUP_WAIT
Configuration Startup Wait
FALSE
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 2 13696 0
Slice Flip Flops 4 27392 0
IOs 26 NA NA
bonded IOBs 0 556 0
GCLKs 3 16 18
DCMs 1 8 12


dcm_1   Digital Clock Manager (DCM)
The digital clock manager module is a wrapper around the DCM primitive which allows it to be used in the EDK tool suite.


dcm_1 IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 CLKIN I 1 ddr_feedback_s
2 CLKFB I 1 dcm_1_FB
3 RST I 1 dcm_0_lock
4 CLK90 O 1 ddr_clk_90_s
5 CLK0 O 1 dcm_1_FB


General
IP Core dcm_module
Version 1.00.c
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
virtex2p
C_CLK0_BUF
Insert a BUFG for CLK0
TRUE
C_CLK180_BUF
Insert a BUFG for CLK180
FALSE
C_CLK270_BUF
Insert a BUFG for CLK270
FALSE
C_CLK2X180_BUF
Insert a BUFG for CLK2X180
FALSE
C_CLK2X_BUF
Insert a BUFG for CLK2X
FALSE
C_CLK90_BUF
Insert a BUFG for CLK90
TRUE
C_CLKDV_BUF
Insert a BUFG for CLKDV
FALSE
C_CLKDV_DIVIDE
CLKDV Divisor
2.0
C_CLKFB_BUF
Insert a BUFG for CLKFB
FALSE
C_CLKFX180_BUF
Insert a BUFG for CLKFX180
FALSE
C_CLKFX_BUF
Insert a BUFG for CLKFX
FALSE
C_CLKFX_DIVIDE
Divisor for the CLKFX Output
1
C_CLKFX_MULTIPLY
Multiply Value of the CLKFX Output
4
 
Name Value
C_CLKIN_BUF
Insert a BUFG for CLKIN
FALSE
C_CLKIN_DIVIDE_BY_2
CLKIN Divide By 2
FALSE
C_CLKIN_PERIOD
Input Clock Period
10.000000
C_CLKOUT_PHASE_SHIFT
Controls Use of Phase Shift
FIXED
C_CLK_FEEDBACK
Clock Feedback Input
1X
C_DESKEW_ADJUST
Amount of Delay in the Feedback Path
SYSTEM_SYNCHRONOUS
C_DFS_FREQUENCY_MODE
Digital Frequency Synthesizer Clock Frequency Mode
LOW
C_DLL_FREQUENCY_MODE
Delay Locked Loop Frequency Mode
LOW
C_DSS_MODE
DSS Mode
NONE
C_DUTY_CYCLE_CORRECTION
Duty Cycle Correction
TRUE
C_EXT_RESET_HIGH
Reset Polarity
0
C_PHASE_SHIFT
Phase Shift
60
C_STARTUP_WAIT
Configuration Startup Wait
FALSE
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 2 13696 0
Slice Flip Flops 4 27392 0
4 input LUTs 1 27392 0
IOs 26 NA NA
bonded IOBs 0 556 0
GCLKs 2 16 12
DCMs 1 8 12


ddr_clk90_inv   Utility Vector Logic
'Simple logic functions, and, or, xor, not.'


ddr_clk90_inv IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Op1 I 1 ddr_clk_90_s
2 Res O 1 ddr_clk_90_n_s


General
IP Core util_vector_logic
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION
Type of Vector Operation To Perform
not
C_SIZE
Size of The Vector
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
4 input LUTs 1 27392 0
IOs 3 NA NA
bonded IOBs 0 556 0


devclk90_inv   Utility Vector Logic
'Simple logic functions, and, or, xor, not.'


devclk90_inv IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Op1 I 1 ddr_dev_clk_90_s
2 Res O 1 ddr_dev_clk_90_s_n


General
IP Core util_vector_logic
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION
Type of Vector Operation To Perform
not
C_SIZE
Size of The Vector
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
4 input LUTs 1 27392 0
IOs 3 NA NA
bonded IOBs 0 556 0


devclk_inv   Utility Vector Logic
'Simple logic functions, and, or, xor, not.'


devclk_inv IP Image
PORT LIST
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
1 Op1 I 1 ddr_dev_clk_s
2 Res O 1 ddr_dev_clk_s_n


General
IP Core util_vector_logic
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION
Type of Vector Operation To Perform
not
C_SIZE
Size of The Vector
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
4 input LUTs 1 27392 0
IOs 3 NA NA
bonded IOBs 0 556 0





Timing Information TOP


Post Synthesis Clock Limits
These are the post synthesis clock frequencies. The critical frequencies are marked with green.
The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system.
MODULE CLK Port MAX FREQ
opb_evoblock_0 OPB_Clk 60.404MHz
microblaze_0 DCACHE_FSL_OUT_CLK 130.638MHz
RS232_Uart_1 OPB_Clk 236.636MHz
ilmb LMB_Clk 341.530MHz
dlmb LMB_Clk 341.530MHz
mb_opb OPB_Clk 341.530MHz
dcm_0 CLKIN 1099.505MHz
dcm_1 CLKIN 1099.505MHz


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