-- user_logic.vhd file for EDK Howto -- A.Greensted library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; entity user_logic is generic ( C_DWIDTH : integer := 32; C_NUM_CE : integer := 4 ); port ( ledPort : out std_logic_vector(3 downto 0); Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic ); end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is signal writeSelect : std_logic_vector(0 to 3); signal readSelect : std_logic_vector(0 to 3); signal data_BUS2IP : std_logic_vector(31 downto 0); signal data_IP2BUS : std_logic_vector(31 downto 0); signal reg0 : std_logic_vector(31 downto 0); signal reg1 : std_logic_vector(31 downto 0); signal reg2 : std_logic_vector(31 downto 0); signal reg3 : std_logic_vector(31 downto 0); function reverseVector (a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'reverse_range); begin for i in a'range loop result((a'length-1)-i) := a(i); end loop; return result; end; begin writeSelect <= Bus2IP_WrCE(0 to 3); readSelect <= Bus2IP_RdCE(0 to 3); -- Assume there will never be a bus error IP2Bus_Error <= '0'; -- Assume a retry will not be needed IP2Bus_Retry <= '0'; -- No timout suspend required IP2Bus_ToutSup <= '0'; -- Always Acknowledge all reads and writes IP2Bus_Ack <= '0' when (Bus2IP_WrCE="0000" and Bus2IP_RdCE="0000") else '1'; -- Reverse the data direction to and from the bus -- This means we can work with the more sensible (31 downto 0) MSB:31, LSB:0 data_BUS2IP <= reverseVector(Bus2IP_Data); IP2Bus_Data <= reverseVector(data_IP2BUS); -- Connect out ledPort (that will connect to some external LEDs) to reg0 ledPort <= reg0(3 downto 0); WriteControl : process (Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk='1') then if (Bus2IP_Reset = '1') then reg0 <= (others => '0'); reg1 <= (others => '0'); reg2 <= (others => '0'); reg3 <= (others => '0'); else case writeSelect is when "1000" => reg0 <= data_BUS2IP; when "0100" => reg1 <= data_BUS2IP; when "0010" => reg2 <= data_BUS2IP; when "0001" => reg3 <= data_BUS2IP; when others => null; end case; end if; end if; end process WriteControl; ReadControl : process(readSelect, reg0, reg1, reg2, reg3) is begin case writeSelect is when "1000" => data_IP2BUS <= reg0; when "0100" => data_IP2BUS <= reg1; when "0010" => data_IP2BUS <= reg2; when "0001" => data_IP2BUS <= reg3; when others => data_IP2BUS <= (others => '0'); null; end case; end process readControl; end IMP;