library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;

entity Main is
    Port ( clk : in std_logic;
           led : out std_logic_vector(3 downto 0));
end Main;

architecture Behavioral of Main is

	attribute LOC : string;
	attribute LOC of clk			: signal is "AE13";
	attribute LOC of led			: signal is "L3 L2 M2 M1";

begin

LedTest : process(clk)

	variable count : std_logic_vector(20 downto 0);
	variable ledOut : std_logic_vector(3 downto 0);

begin

	if (clk'event and clk='1') then

		count := count + 1;

		if (count = "00000000000000000000") then

			ledOut := ledOut + 1;

		end if;

	end if;

	led <= ledOut;

end process ledTest;

end Behavioral;